Revision as of 22:23, November 18, 2014

Funtoo Linux Sub-Architectures

This page provides an overview of Funtoo Linux sub-architectures (also called subarches,) designed for quick and easy reference. While this information is available in other places, such as Wikipedia, it often takes some time to study and cross-reference the various articles to get a good understanding of each type of sub-architecture, and this information generally isn't all collected neatly in one place. That is the purpose of this page. When possible, links to more detailed Wikipedia pages are provided. You are encouraged to help maintain this page as well as the Wikipedia articles referenced here.

64-bit Suport (Generic)

generic_64

CFLAGS: -mtune=generic -O2 -pipe
CHOST: x86_64-pc-linux-gnu
USE: mmx sse sse2

The generic_64 subarch is designed to support 64-bit PC-compatible CPUs, such as the AMD K8-series processors, which were introduced in late 2003. They were notable as the first processors that supported the AMD64 (also called X86-64) 64-bit instruction set for PC-compatible systems, which was introduced as a backwards-compatible 64-bit alternative to Intel's IA-64 architecture. Intel followed suit and also began supporting this 64-bit instruction set, which they called "Intel 64", by releasing X86-64 64-bit compatible CPUs from mid-2004 onwards (See Intel 64 implementations.)

AMD desktop 64-bit CPUs include the Athlon 64, Athlon 64 FX, Athlon 64 X2, Athlon X2, Turion 64, Turion 64 X2 and Sempron series processors. AMD server processors were released under the Opteron brand and have codenames SledgeHammer, Venus, Troy, Athens, Denmark, Italy, Egypt, Santa Ana and Santa Rosa. All Opterons released through late 2006 were based on the K8 microarchitecture with original X86-64 instructions.

64-bit AMD Processors

amd64-k10

CFLAGS: -march=amdfam10 -O2 -pipe
CHOST: x86_64-pc-linux-gnu
USE: mmx sse sse2 sse3 3dnow 3dnowext

The amd64-k10 subarch provides support for the AMD Family 10h processors, which were released in late 2007 as a successor to the AMD K8 series processors.

Desktop amd64-k10 CPUs include AMD Phenom, AMD Phenom II and AMD Athlon II. Server CPUs include Opterons with codenames Budapest, Barcelona, Suzuka, Shanghai, Istanbul, Lisbon, and Magny-Cours. A full listing of amd64-k10 Opteron models can be found here.

amd64-bulldozer

CFLAGS: -march=bdver1 -O2 -pipe
CHOST: x86_64-pc-linux-gnu
USE: mmx sse sse2 sse3 sse4 3dnow 3dnowext

The amd64-bulldozer subarch supports the AMD bulldozer microarchitecture CPUs, which were released from late 2011 through the first quarter of 2012 as a replacement for the K10 microarchitecture CPUs. Bulldozer desktop CPUs use the AM3+ socket and server CPUs use the G34 socket.

Desktop bulldozer CPUs include the Zambezi FX-series CPUs. Server bulldozer CPUs include Opterons with codenames Zurich (Opteron 3200-series), Valencia (Opteron 4200-series) and Interlagos (Opteron 6200 series). A complete list of Opteron models can be found here..

amd64-piledriver

CFLAGS: -march=bdver2 -O2 -pipe
CHOST: x86_64-pc-linux-gnu
USE: mmx sse sse2 sse3 sse4 3dnow 3dnowext

The amd64-piledriver subarch supports the AMD Piledriver microarchitecture produced by AMD from mid-2012 through 2015, which is the successor to the AMD bulldozer microarchitecture. Piledriver CPUs and APUs are available that use the FM2 socket. Desktop Piledriver CPUs use the AM3+ socket. Server Piledriver CPUs use a variety of sockets, including AM3+, C32 and G34.

Desktop piledriver CPU and APUs include FX-series with codename Vishera (FX-8350, FX-8370), A-series with codename Trinity (A6-5400K, A10-5800K) and A-series with codename Richland.

Server piledriver CPUs include Opterons with codenames Delhi (Opteron 3300-series, AM3+), Seoul (Opteron 4300-series, C32) and Abu Dhabi (Opteron 6300-series, G34). A full listing of Opteron models is available here.

Piledriver adds several new instructions over bulldozer, so AMD bulldozer systems cannot run amd64-piledriver-optimized stages. However, this subarch is instruction-compatible with its successor, the, so amd64-piledriver stages can run on amd64-steamroller systems, and vice versa.

amd64-steamroller

CFLAGS: -march=bdver3 -O2 -pipe
CHOST: x86_64-pc-linux-gnu
USE: mmx sse sse2 sse3 sse4 3dnow 3dnowext

The amd64-steamroller subarch supports the AMD steamroller microarchitecture, produced from early 2014. It is the successor to the AMD Piledriver microarchitecture. Steamroller APUs are available that use the FM2+ socket and FP3 socket (mobile.)

Desktop steamroller APUs include the A-Series with codename Kaveri, such as the quad-core AMD A10-7850K APU. Steamroller APUs are also available in mobile versions. Server steamroller APUs will include the Berlin APUs, which are expected to be released some time in 2015.

Amd64-steamroller subarches are instruction-compatible with amd64-piledriver, but add new instructions over amd64-bulldozer.

amd64-jaguar

CFLAGS: -march=btver2 -O2 -pipe
CHOST: x86_64-pc-linux-gnu
USE: mmx sse sse2 sse3 sse4 3dnow 3dnowext

The amd64-jaguar (also called AMD Family 16h) subarch supports the AMD jaguar microarchitecture, which is targeted at low-power devices, including notebooks, tablets and small form-factor desktops and servers. It is perhaps most well-known for being the microarchitecture used for the Playstation 4 and Xbox One, which each use custom 8-core Jaguar APUs. Socketed Jaguar APUs use the AM1 socket, and FT3 socket for mobile devices. G-series "system on a chip" (SoC) APUs are available for non-socketed devices such as tablets and embedded system boards.

Desktop Jaguar APUs include the Kabini A-series APUs and Temash E-series APUs, such as the Athlon 5150 and 5350 APUs, and Sempron 2650 and 3850.

Amd64-jaguar subarches use the MOVBE instruction which is not available on amd64-bulldozer, amd64-piledriver or amd64-steamroller. They are thus not instruction-compatible with any of these subarches.

64-bit Intel Processors

corei7

CFLAGS: -march=corei7 -O2 -pipe
CHOST: x86_64-pc-linux-gnu
USE: mmx sse sse2 sse3 ssse3 sse4

Introduced November of 2008, the corei7 subarch supports the Nehalem, Sandy Bridge, Ivy Bridge, and Haswell microarchitectures.

core2_64

CFLAGS: -march=core2 -O2 -pipe
CHOST: x86_64-pc-linux-gnu
USE: mmx sse sse2 sse3 ssse3

The core2_64 subarch supports 64-bit-capable Intel Core 2 Processors, which includes some processors of the Core and all processors of the Penryn microarchitecture. All "Core 2" branded processors are 64-bit-capable. These processors were introduced in July of 2006 and were phased out in July of 2011, in favor of Nehalem-based processors.

For a full list of 64-bit capable Core 2 processors, see this link.

The 64-bit capable Core 2-branded CPUs include: "Conroe"/"Allendale" (dual-core for desktops), "Merom" (dual-core for laptops), "Merom-L" (single-core for laptops), "Kentsfield" (quad-core for desktops), and the updated variants named "Wolfdale" (dual-core for desktops), "Penryn" (dual-core for laptops), and "Yorkfield" (quad-core for desktops). (Note: For the server and workstation "Woodcrest", "Tigerton", "Harpertown" and "Dunnington" CPUs see the Xeon brand.)

atom_64

CFLAGS: -O2 -fomit-frame-pointer -march=atom -pipe -mno-movbe
CHOST: x86_64-pc-linux-gnu
USE: mmx sse sse2 sse3

The Intel Atom Processor is the common name for Intel's Bonnell microarchitecture, which represents a partial revival of the principles used in earlier Intel designs such as P5 and the i486, with the sole purpose of enhancing the performance per watt ratio. Successor to the Intel A100 series (Stealey), which was derived from the Pentium M, the Intel Atom has been produced since 2008. Targeted at low-power devices, Atom processors can be found in a wide range of notebooks, tablets and small form-factor desktops and servers.

The atom_64 sub-architecture supports 64-bit capable Intel Atom CPUs. The first 64-bit capable Intel Atom CPUs were the Intel Atom 230 and 330, released in late 2008. However, Intel also continued to produce new 32-bit Atom Processors after this date. For example, the Atom N2xx series Atom Diamondville models cannot support 64-bit operation, while the 2xx and 3xx Diamondville, Pineview, Cedarview and Centerton can. A full list of 64-bit capable Intel Atom Processors can be seen here.

Important

For 64-bit support to be functional, a 64-bit capable Atom Processor must be paired with a processor, chipset, and BIOS that all support Intel 64. If not all hardware supports 64-bit, then you must use the atom_32 subarch instead.

32-bit Suport (Generic)

generic_32

CFLAGS: -mtune=generic -O2 -pipe
CHOST: i686-pc-linux-gnu
USE:

32-bit AMD Processors

amd64-k8_32

CFLAGS: -O2 -fomit-frame-pointer -march=k8 -pipe
CHOST: i686-pc-linux-gnu
USE: mmx sse sse2 3dnow 3dnowext

athlon-xp

CFLAGS: -O2 -fomit-frame-pointer -march=athlon-xp -pipe
CHOST: i686-pc-linux-gnu
USE: mmx sse 3dnow

32-bit Intel Processors

atom_32

CFLAGS: -O2 -fomit-frame-pointer -march=atom -pipe -mno-movbe
CHOST: i686-pc-linux-gnu
USE: mmx sse sse2 sse3

core2_32

CFLAGS: -march=core2 -O2 -fomit-frame-pointer -pipe
CHOST: i686-pc-linux-gnu
USE: mmx sse sse2 sse3 ssse3

i686

CHOST: i686-pc-linux-gnu
CFLAGS: -O2 -march=i686 -mtune=generic -pipe
USE:

pentium4

CFLAGS: -O2 -fomit-frame-pointer -march=pentium4 -pipe
CHOST: i686-pc-linux-gnu
USE: mmx sse sse2

32-bit ARM (Advanced RISC Machines) Processors

armv5te

CFLAGS: -O2 -pipe -march=armv5te 
CHOST: armv5tel-softfloat-linux-gnueabi 
USE:

armv6j_hardfp

CFLAGS: -O2 -pipe -march=armv6j -mfpu=vfp -mfloat-abi=hard
CHOST: armv6j-hardfloat-linux-gnueabi
USE:

armv7a_hardfp

CFLAGS: -O2 -pipe -march=armv7-a -mfpu=vfpv3-d16 -mfloat-abi=hard
CHOST: armv7a-hardfloat-linux-gnueabi
USE:

@@ Line 12: / Line 12: @@
 USE: mmx sse sse2
 </console>
-Produces code optimized for the most common AMD64/EM64T processors. As new processors are deployed in the marketplace, the behavior of this option will change. Therefore, if you upgrade to a newer version of GCC, code generation controlled by this option will change to reflect the processors that are most common at the time that version of GCC is released.
 The '''generic_64''' subarch is designed to support 64-bit PC-compatible CPUs, such as the [[Wikipedia:AMD_K8|AMD K8-series processors]], which were introduced in late 2003. They were notable as the first processors that supported the [[Wikipedia:X86-64|AMD64 (also called X86-64) 64-bit instruction set]] for PC-compatible systems, which was introduced as a backwards-compatible 64-bit alternative to Intel's IA-64 architecture. Intel followed suit and also began supporting this 64-bit instruction set, which they called "[[Wikipedia:X86-64#Intel_64|Intel 64]]", by releasing X86-64 64-bit compatible CPUs from mid-2004 onwards (See [[Wikipedia:X86-64#Intel_64_implementations|Intel 64 implementations]].)
@@ Line 27: / Line 25: @@
 USE: mmx sse sse2 sse3 3dnow 3dnowext
 </console>
-CPUs based on AMD Family 10h cores with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, SSE3, SSE4A, 3DNow!, enhanced 3DNow!, ABM and 64-bit instruction set extensions.)
 The '''amd64-k10''' subarch provides support for the [[Wikipedia:AMD_10h|AMD Family 10h processors]], which were released in late 2007 as a successor to the AMD K8 series processors.
@@ Line 40: / Line 36: @@
 USE: mmx sse sse2 sse3 sse4 3dnow 3dnowext
 </console>
-CPUs based on AMD Family 15h cores with x86-64 instruction set support. (This supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.)
 The '''amd64-bulldozer''' subarch supports the [[Wikipedia:Bulldozer (microarchitecture)|AMD bulldozer microarchitecture]] CPUs, which were released from late 2011 through the first quarter of 2012 as a replacement for the [[Wikipedia:AMD_10h|K10 microarchitecture]] CPUs.
@@ Line 54: / Line 48: @@
 USE: mmx sse sse2 sse3 sse4 3dnow 3dnowext
 </console>
-AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets BMI, TBM, F16C, FMA, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.)
 The '''amd64-piledriver''' subarch supports the [[Wikipedia:Piledriver (microarchitecture)|AMD Piledriver microarchitecture]] produced by AMD from mid-2012 through 2015, which is the successor to the [[Wikipedia:Bulldozer (microarchitecture)|AMD bulldozer microarchitecture]].
@@ Line 72: / Line 64: @@
 USE: mmx sse sse2 sse3 sse4 3dnow 3dnowext
 </console>
-AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets BMI, TBM, F16C, FMA, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.)
 The '''amd64-steamroller''' subarch supports the  [[Wikipedia:Steamroller (microarchitecture)|AMD steamroller microarchitecture]], produced from early 2014. It is the successor to the [[Wikipedia:Piledriver (microarchitecture)|AMD Piledriver microarchitecture]].
@@ Line 88: / Line 78: @@
 USE: mmx sse sse2 sse3 sse4 3dnow 3dnowext
 </console>
-CPUs based on AMD Family 16h cores with x86-64 instruction set support. This includes MOVBE, F16C, BMI, AVX, PCL_MUL, AES, SSE4.2, SSE4.1, CX16, ABM, SSE4A, SSSE3, SSE3, SSE2, SSE, MMX and 64-bit instruction set extensions.
 The '''amd64-jaguar''' (also called AMD Family 16h) subarch supports the  [[Wikipedia:Jaguar (microarchitecture)|AMD jaguar microarchitecture]], which is targeted at low-power devices, including notebooks, tablets and small form-factor desktops and servers. It is perhaps most well-known for being the microarchitecture used for the [[Wikipedia:Playstation 4|Playstation 4]] and [[Wikipedia:Xbox One|Xbox One]], which each use custom 8-core Jaguar APUs.
@@ Line 106: / Line 94: @@
 USE: mmx sse sse2 sse3 ssse3 sse4
 </console>
-Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 instruction set support.
 Introduced November of 2008, the '''corei7''' subarch supports the [[Wikipedia:Nehalem_(microarchitecture)|Nehalem]], [[Wikipedia:Sandy_Bridge_(microarchitecture)|Sandy Bridge]], [[Wikipedia:Ivy_Bridge_(microarchitecture)|Ivy Bridge]], and [[Wikipedia:Haswell_(microarchitecture)|Haswell]] microarchitectures.
@@ Line 116: / Line 103: @@
 USE: mmx sse sse2 sse3 ssse3
 </console>
-Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support.
 The '''core2_64''' subarch supports 64-bit-capable [[Wikipedia:Intel_Core_2|Intel Core 2 Processors]], which includes ''some'' processors of the [[Wikipedia:Intel Core (microarchitecture)|Core]] and all processors of the [[Wikipedia:Penryn_(microarchitecture)|Penryn]] microarchitecture. All "Core 2" branded processors are 64-bit-capable. These processors were introduced in July of 2006 and were phased out in July of 2011, in favor of  [[Wikipedia:Nehalem_(microarchitecture)|Nehalem-based]] processors.
@@ Line 131: / Line 116: @@
 USE: mmx sse sse2 sse3
 </console>
-Intel Atom CPU with 64-bit extensions MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support.
 The Intel Atom Processor is the common name for Intel's  [[Wikipedia:Bonnell_(microarchitecture)|Bonnell microarchitecture]],  which represents a partial revival of the principles used in earlier Intel designs such as P5 and the i486, with the sole purpose of enhancing the performance per watt ratio.  Successor to the [[Wikipedia:Stealey_(microprocessor)|Intel A100 series (Stealey)]], which was derived from the [[Wikipedia:Pentium_M|Pentium M]], the Intel Atom has been produced since 2008. Targeted at low-power devices, Atom processors can be found in a wide range of notebooks, tablets and small form-factor desktops and servers.
@@ Line 147: / Line 130: @@
 USE:
 </console>
-Produces code optimized for the most common IA32 processors. If new processors are deployed in the marketplace, the behavior of this option will change. Therefore, if you upgrade to a newer version of GCC, code generation controlled by this option will change to reflect the processors that are most common at the time that version of GCC is released.
 == 32-bit AMD Processors ==
@@ Line 164: / Line 145: @@
 USE: mmx sse 3dnow
 </console>
-Improved AMD Athlon CPU with MMX, 3DNow!, enhanced 3DNow! and full SSE instruction set support.
 == 32-bit Intel Processors ==
@@ Line 188: / Line 167: @@
 USE:
 </console>
-Only the Pentium Pro instruction set is used, so the code runs on all i686 family chips.
 === pentium4 ===
@@ Line 197: / Line 174: @@
 USE: mmx sse sse2
 </console>
-Intel Pentium 4 CPU with MMX, SSE and SSE2 instruction set support.
 == 32-bit ARM (Advanced RISC Machines) Processors ==

Difference between revisions of "Subarches"